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datasheet real-time clock with serial i 2 c interface IDT1339 idt? real-time clock with serial i 2 c interface 1 IDT1339 rev s 031014 general description the IDT1339 serial real-time clock (rtc) is a low-power clock/date device with two programmable time-of-day alarms and a programmable square-wave output. address and data are transferred serially through an i 2 c bus. the clock/date provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with am/pm indicator. the IDT1339 has a built-in power-sense circuit that detects power failures and automatically switches to the backup supply, maintaining time, date, and alarm operation. applications ? handhelds (gps, pos terminals) ? consumer electronics (set-top box, digital recording, network applications) ? office (fax/printers, copiers) ? medical (glucometer, medicine dispensers) ? telecomm (routers, switches, servers) ? other (thermostats, vending machines, modems, utility meters) features ? real-time clock (rtc) counts seconds, minutes, hours, day, date, month, and year with leap-year compensation valid up to 2100 ? packaged in 8-pin msop, 8-pin soic, or 16-pin soic (surface-mount package with an integrated crystal) ? fast mode i 2 c serial interface ? two time-of-day alarms ? programmable square-wave output ? oscillator stop flag ? automatic power-fail detect and switch circuitry ? trickle-charge capability ? industrial temperature range (-40 to +85c) ? underwriters laboratory (ul) recognized block diagram vcc gnd v backup scl sda crystal inside package for 16-pin soic only x1 x2 1 hz/4.096 khz/ 8.192 khz/32.768 khz sqw/int power control i 2 c interface 32.768 khz oscillator and divider control logic mux/ buffer clock, calendar counter 1 byte control 7 bytes buffer trickle charger byte 7 bytes alarm trickle charger 1 byte status
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 2 IDT1339 rev s 031014 pin assignment (8-pin msop/8-pin soic) pin assignment (16-pin soic) pin descriptions x1 scl sqw/int gnd vcc 1 2 3 4 8 7 6 5 sda x2 v backup idt 1339 16 1 15 2 14 3 13 4 5 6 7 8 9 10 12 11 scl vcc nc nc nc nc nc nc nc nc nc nc sda gnd sqw/int v backup idt 1339c pin number pin name pin description/function msop soic 1 ? x1 connections for standard 32.768 khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (cl) of 7 pf. an external 32.768 khz oscillator can also drive the IDT1339. in this conf iguration, the x1 pin is connected to the external oscillator signal and the x2 pin is left floating. 2? x2 314v backup backup supply input. supply voltage must be held between 1.3 v and 3.7 v for proper operation. this pin can be connected to a primary cell, such as a lithium button cell. additionally, this pin can be connected to a re chargeable cell or a super cap that can be charged using the trickle charger circuit. dio des placed in series between the backup source and the vbat pin may prevent proper operation. if a backup supply is not required, vbat must be connected to ground. ul recognized to ensure against reverse charged current when used with a lithium cell. 4 15 gnd connect to ground. dc power is provided to the device on these pins. 5 16 sda serial data input/output. sda is the input/output pin for the i 2 c serial interface. the sda pin is an open-drain output and requires an external pull-up resistor (2 k ? typical). 6 1 scl serial clock input. scl is used to synchronize data movement on the serial interface. it is an open-drain output and requires an external pull-up resistor (2 k ? typical). 72sqw/int square-wave/interrupt output. programmable square-wave or interrupt output signal. the sqw/int pin is an open-drain output and requires an external pull-up resistor (10 k ? typical). 83 v cc primary power supply. when voltage is applied within normal limits, the device is fully accessible and data can be written and read. ? 4 - 13 nc no connect. these pins are unused and must be connected to ground.
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 3 IDT1339 rev s 031014 typical operating circuit detailed description the following sections discuss in detail the oscillator block, power control block, clock/calendar register, alarms, trickle charger, and serial i 2 c block. oscillator block selection of the right crystal, correct load capacitance and careful pcb layout are important for a stable crystal oscillator. due to the optimization for the lowest possible current in the design for these oscillators, losse s caused by parasitic currents can have a significant impact on the overall oscillator performance. extra care needs to be taken to maintain a certain quality and cleanliness of the pcb. crystal selection the key parameters when selecting a 32 khz crystal to work with IDT1339 rtc are: ? recommended load capacitance ? crystal effective series resistance (esr) ? frequency tolerance effective load capacitance please see diagram below for effective load capacitance calculation. the effective load capacitance (cl) should match the recommended load capacitance of the crystal in order for the crystal to oscilla te at its specified parallel resonant frequency with 0ppm frequency error. in the above figure, x1 and x2 are the crystal pins of our device. cin1 and cin2 are the internal capacitors which include the x1 and x2 pin capacitance. cex1 and cex2 are the external capacitors that are needed to tune the crystal frequency. ct1 and ct2 are the pcb trace capacitances between the crystal and the device pins. cs is the shunt capacitance of the crystal (as specified in the crystal manufacturer's datasheet or measured using a network analyzer). note : IDT1339csri integrates a standard 32.768 khz (20ppm) crystal in the package and contributes an additional frequency error of 10ppm at nominal v cc (+3.3 v) and t a = +25c. cpu x1 x2 v cc sqw/int v backup gnd sda scl crystal IDT1339 + - v cc r pu 2k v cc v cc 10k r pu 2k 12 6 5 7 3 4 8
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 4 IDT1339 rev s 031014 esr (effective series resistance) choose the crystal with lower esr. a low esr helps the crystal to start up and stabilize to the correct output frequency faster compared to high esr crystals. frequency tolerance the frequency tolerance for 32khz crystals should be specified at nominal temperature (+25c) on the crystal manufacturer datasheet. the crystals used with IDT1339 typically have a frequency tolerance of 20ppm at +25c. specifications for a typical 32 khz crystal used with our device are shown in the table below. pcb design consideration ? signal traces between idt device pins and the crystal must be kept as short as possible. this minimizes parasitic capacitance and sensitivity to crosstalk and emi. note that the trace capacitances play a role in the effective crystal load capacitance calculation. ? data lines and frequently switching signal lines should be routed as far away from the crystal connections as possible. crosstalk from these signals may disturb the oscillator signal. ? reduce the parasitic capacitance between x1 and x2 signals by routing them as far apart as possible. ? the oscillation loop current flows between the crystal and the load capacitors. this signal path (crystal to cl1 to cl2 to crystal) should be kept as short as possible and ideally be symmetric. the ground connections for both capacitors should be as cl ose together as possible. never route the ground connection between the capacitors all around the crystal, because this long ground trace is sensitive to crosstalk and emi. ? to reduce the radiation / co upling from oscillator circuit, an isolated ground island on the gnd layer could be made. this ground island can be connected at one point to the gnd layer. this helps to keep noise generated by the oscillator circuit locally on this separated island. the ground connections for the load capacitors and the oscillator should be conn ected to this island. pcb layout pcb assembly, soldering and cleaning board-assembly production process and assembly quality can affect the performance of the 32 khz oscillator. depending on the flux material used, the soldering process can leave critical residues on the pcb surface. high humidity and fast temperature cycles that cause humidity condensation on the printed circuit board can create process residuals. these process residuals cause the insulation of the sensitive o scillator signal lines towards each other and neighboring signals on the pcb to decrease. high humidity can lead to moisture condensation on the surface of the pcb and, together with process residuals, reduce the surface resistivity of the board. flux residuals on the board can cause leakage current paths, especially in humid environments. thorough pcb cleaning is therefore highly recommended in order to achieve maximum performance by removing flux residuals from the board after assembly. in general, reduction of losses in the oscillator circuit leads to better safe ty margin and reliability. power control the power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the v cc level. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . the registers are maintained from the v backup source until v cc is returned to nominal levels (table 1). after v cc returns above v pf , read and write access is allowed after t rec (see the ?power-up/down timing? diagram). parameter symbol min typ max units nominal freq. f o 32.768 khz series resistance esr 50 k ? load capacitance c l 7pf 1339
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 5 IDT1339 rev s 031014 table 1. power control power-up/down timing table 2. power-up/down characteristics ambient temperature -40 to +85 ? c note 1: this delay applies only if the osc illator is running. if the oscillator is di sabled or stopped, no power-up delay occurs. note 2: measured at typ vbat level. supply condition read/write access powered by v cc < v pf , v cc < v backup no v backup v cc < v pf , v cc > v backup no v cc v cc > v pf , v cc < v backup ye s v cc v cc > v pf , v cc > v backup ye s v cc parameter symbol conditions min. typ. max. units recovery at power-up t rec (see note 1) 2 ms v cc fall time; v pf(max) to v pf(min) t vccf (see note 2) 3 ms v cc rise time; v pf(min) to v pf(max) t vccr 0s
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 6 IDT1339 rev s 031014 address map table 3 (timekeeper registers) shows the address map for the IDT1339 registers. during a multibyte access, when the address pointer reaches the end of the register space (10h), it wraps around to location 00h. on an i 2 c start, stop, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to re-read the registers in case of an update of the main registers during a read. table 3. timekeeper registers note : unless otherwise specified, the state of the registers are not defined when power is first applied or when v cc and v backup falls below the v backup(min) . address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 10 seconds seconds seconds 00 - 59 01h 0 10 minutes minutes minutes 00 - 59 02h 0 12/24 am /pm 10 hour hour hours 1 - 12 + am/pm 00 - 23 10 hour 03h00000 day day 1 - 7 04h 0 0 10 date date date 01 - 31 05h century 0 0 10 month month month/century 01 - 12 + century 06h 10 year year year 00 - 99 07h a1m1 10 seconds seconds alarm 1 seconds 00 - 59 08h a1m2 10 minutes minutes alarm 1 minutes 00 - 59 09h a1m3 12/24 am /pm 10 hour hour alarm 1 hours 1 - 12 + am/pm 00 - 23 10 hour 0ah a1m4 dy/dt 10 date day, date alarm 1 day, alarm 1 date 1 - 7, 1 - 31 0bh a2m2 10 minutes minutes alarm 2 minutes 00 - 59 0ch a2m3 12/24 am /pm 10 hour hour alarm 2 hours 1 - 12 + am/pm 00 - 23 10 hour 0dh a2m4 dy/dt 10 date day, date alarm 2 day, alarm 2 date 1 - 7, 1 - 31 0eh eosc 0 bbsqi rs2 rs1 intcn a2ie a1ie control 0fhosf00000a2fa1fstatus 10h tcs3 tcs2 tcs1 tcs0 ds1 ds0 ro ut1 rout0 trickle charger
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 7 IDT1339 rev s 031014 time and date operation the time and date information is obtained by reading the appropriate register bytes. table 3 shows the rtc registers. the time and date are set or initialized by writing the appropriate register bytes. the contents of the time and date registers are in the bcd format. the IDT1339 can be run in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am /pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). all hours values, including the alarms, must be re-entered whenever the 12/24 -hour mode bit is changed. the century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. the day-of-week register increments at midnight. values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals sunday, then 2 equals monday and so on). illogical time and date entries result in undefined operation. when reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop, and when the address pointer rolls over to zero. the countdown chain is reset whenever the seconds register is written. write transfers occurs on the acknowledge pulse from the device. to avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within one second. if enabled, the 1 hz square-wave output transitions high 500 ms after the seconds data transfer, provided the oscillator is already running. alarms the IDT1339 contains two time of day/date alarms. alarm 1 can be set by writing to registers 07h to 0ah. alarm 2 can be set by writing to registers 0bh to 0dh. the alarms can be programmed (by the alarm enable and intcn bits of the control register) to activate the sqw/int output on an alarm match condition. bit 7 of each of the time of day/date alarm registers are mask bits (table 4). when all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h to 06h match the values stored in the time of day/date alarm registers. the alarms can also be programmed to repeat every second, minute, hour, day, or date. table 4 shows the possible settings. configurations not lis ted in the table result in illogical operation. the dy/dt bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. if dy/dt is written to a logic 0, the alarm is the result of a match with date of the month. if dy/dt is written to a logic 1, the alarm is the result of a match with day of the week. the device checks for an alarm match once per second. when the rtc register values match alarm register settings, the corresponding alarm flag ?a1f? or ?a2f? bit is set to logic 1. if the corresponding alarm interrupt enable ?a1ie? or ?a2ie? is also set to logic 1 and the intcn bit is set to logic 1, the alarm condition activates the sqw/int signal. if the bbsqi bit is set to 1, the int output activates while the part is being powered by v backup . the alarm output remains active until the alarm flag is cleared by the user.
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 8 IDT1339 rev s 031014 table 4. alarm mask bits special-purpose registers the IDT1339 has two additional registers (control and status) that control the rtc, alarms, and square-wave output. control register (0eh) bit 7: enable oscillator (eosc ). this bit when set to logic 0 starts the o scillator. when this bit is set to a logic 1, the oscillator is stopped. this bit is enabled (logic 0) when power is first applied. bit 5: battery-backed square-wave and interrupt enable (bbsqi). this bit when set to a logic 1 enables the square wave or interrupt output when v cc is absent and the IDT1339 is being powered by the v backup pin. when bbsqi is a logic 0, the sqw/int pin goes high impedance when v cc falls below the power-fail trip point. this bit is disabled (logic 0) when power is first applied. bits 4 and 3: rate select (rs2 and rs1). these bits control the frequency of the square-wave output when the square wave has been enabled. table 5 shows the square-wave frequencies that can be selected with the rs bits. these bits are both set to logic 1 (32 khz) when power is first applied. dy/dt alarm 1 register mask bits (bit 7) alarm rate a1m4 a1m3 a1m2 a1m1 x1111alarm once per second. x1110alarm when seconds match. x1100alarm when minutes and seconds match. x1000alarm when hours, minutes, and seconds match. 00000alarm when date, hours, minutes, and seconds match. 10000alarm when day, hours, minutes, and seconds match. dy/dt alarm 2 register mask bits (bit 7) alarm rate a2m4 a2m3 a2m2 x 1 1 1 alarm once per minute (00 sec. of every min.). x 1 1 0 alarm when minutes match. x 1 0 0 alarm when hours and minutes match. 0 0 0 0 alarm when date, hours, and minutes match. 1 0 0 0 alarm when day, hours, and minutes match. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc 0 bbsqi rs2 rs1 intcn a2ie a1ie
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 9 IDT1339 rev s 031014 table 5. sqw/int output bit 2: interrupt control (intcn). this bit controls the relationship between the two alarms and the interrupt output pins. when the intcn bit is set to logic 1, a match between the timekeeping registers and the alarm 1 or alarm 2 registers activate the sqw/int pin (provided that the alarm is enabled) . when the intcn bit is set to logic 0, a square wave is output on the sqw/int pin. this bit is set to logic 0 when power is first applied. bit 1: alarm 2 interrupt enable (a2ie). when set to a logic 1, this bit permits the alarm 2 flag (a2f) bit in the status register to assert sqw/int (when intcn = 1). when the a2ie bit is set to logic 0 or intcn is set to logic 0, the a2f bit does not initiate an interrupt signal. the a2ie bit is disabled (logic 0) when power is first applied. bit 0: alarm 1 interrupt enable (a1ie). when set to logic 1, this bit permits the alarm 1 flag (a1f) bit in the status register to assert sqw/int (when intcn = 1). when the a1ie bit is set to logic 0 or intcn is set to logic 0, the a1f bit does not initiate an interrupt signal. the a1ie bi t is disabled (logic 0) when power is first applied. status register (0fh) bit 7: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the valid ity of the clock and date data. this bit is edge triggered and is set to logic 1 when the oscillato r stops. the following are examples of conditions that ca n cause the osf bit to be set: 1) the first time power is applied. 2) the voltage on both v cc and v backup are insufficient to support oscillation. 3) the eosc bit is turned off. 4) external influences on the crystal (e.g., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. this bit can only be written to a logic 0. bit 1: alarm 2 flag (a2f). a logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. if the a2ie bit is a logic 1 and the intcn bit is set to a logic 1, the sqw/int pin is also asserted. a2f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. bit 0: alarm 1 flag (a1f). a logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. if the a1ie bit is a logic 1 and the intcn bit is set to a logic 1, the sqw/int pin is also asserted. a1f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. intcn rs2 rs1 sqw/int output a2ie a1ie 000 1 hz xx 0 0 1 4.096 khz x x 0 1 0 8.192 khz x x 0 1 1 32.768 khz x x 1xx a1f 01 1xx a2f 10 1xx a2f + a1f 11 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 osf00000a2fa1f
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 10 IDT1339 rev s 031014 trickle charger register (10h) programmable trickle charger the simplified ?programmable trickle charger? schematic shows the basic components of the trickle charger. the trickle-charge select (tcs) bits (bits 4 to 7) control the selection of the trickle charger. to prevent accidental enabling, on ly a pattern of 1010 on the tcs bits enables the trickle charger. all other patterns disable the trickle charger. the trickle charger is disabled when power is first applied. the diode-select (ds) bits (bits 2 and 3) select whether or not a diode is connected between v cc and v backup . the rout bits (bits 0 and 1) select the value of the resistor connected between v cc and v backup . table 6 shows the bit values. table 6. trickle charger register (10h) warning: the rout value of 250 ? must not be selected whenever v cc is greater than 3.63 v. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout 1 rout 0 xxx x 0 0 x xdisabled xxx x 1 1 x xdisabled xxx x x x 0 0disabled 1 0 1 0 0 1 0 1 no diode, 250 ? resistor 1 0 1 0 1 0 0 1 one diode, 250 ? resistor 1 0 1 0 0 1 1 0 no diode, 2k ? resistor 1 0 1 0 1 0 1 0 one diode, 2k ? resistor 1 0 1 0 0 1 1 1 no diode, 4k ? resistor 1 0 1 0 1 0 1 1 one diode, 4k ? resistor 0 0 0 0 0 0 0 0 initial power-up values
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 11 IDT1339 rev s 031014 the user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. the maximum charging current ca n be calculated as illustrated in the following example. assume that a 3.3 v system power supply is applied to v cc and a super cap is connected to v backup . also assume that the trickle charger has been enabled with a diode and resistor r2 between v cc and v backup . the maximum current i max would therefore be calculated as follows: i max = (3.3 v - diode drop) / r2 (3.3 v - 0.7 v) / 2k ? 1.3 ma as the super cap or battery charges, the voltage drop between v cc and v backup decreases and therefore the charge current decreases. i 2 c serial data bus the IDT1339 supports the i 2 c bus protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred to as slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the IDT1339 operates as a slave on the i 2 c bus. within the bus specifications, a standard mode (100 khz cycle rate) and a fast mode (400 khz cycle rate) are defined. the IDT1339 works in both modes. connections to the bus are made via the open-drain i/o lines sda and scl. the following bus protocol has been defined (see the ?data transfer on i 2 c serial bus? figure): ? data transfer may be initiate d only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the cl ock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. timeout: timeout is where a slave device resets its interface whenever clock goes low for longer than the timeout, which is typically 35 msec. this added logic deals with slave errors and recovering from those errors. when timeout occurs, the slave interfac e should re-initialize itself and be ready to receive a communication from the master, but it will expect a start prior to any new communication.
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 12 IDT1339 rev s 031014 data transfer on i 2 c serial bus depending upon the state of the r/w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data is transferred with the most significant bit (msb) first. 2) data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. this is followed by the slave transmitting a number of data bytes. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. data is transferred with the most significant bit (msb) first. the IDT1339 can operate in the following two modes: 1) slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit (see the ?data write?slave receiver mode? figure). the slave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7-bit IDT1339 address, which is 1101000, followed by the direction bit (r/w ), which is 0 for a write. after receiving and decoding the slave address byte the slave outputs an acknowledge on the sda line. after the IDT1339 acknowledges the slave address + write bit, the master transmits a register address to the IDT1339. this sets the register pointer on the IDT1339, with the IDT1339 acknowledging the transfer. the master may then transmit zero or more bytes of data, with the IDT1339 acknowledging each byte received. the address pointer increments after each data byte is transferred. the master generates a stop condition to terminate the data write. 2) slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the IDT1339 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer (see the ?data read?slave transmitter mode? figure). the slave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7-bit IDT1339 address, which is 1101000, followed by the direction bit (r/w ), which is 1 for a read. after receiving and decoding the slave address byte the slave outputs an acknowledge on the sda line. the IDT1339 then begins to transmit data starting with the register address pointed to by
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 13 IDT1339 rev s 031014 the register pointer. if the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. the address pointer is incremented after each byte is transferred. the IDT1339 must receive a ?not acknowledge? to end a read. data write ? slave receiver mode data read (from current pointer location) ? sla ve transmitter mode data read (write pointer, then read) ? slave receive and transmit
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 14 IDT1339 rev s 031014 handling, pcb layout, and assembly the IDT1339 package contains a quartz tuning-fork crystal. pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avioded. ultarsonic cleaning equipment should be avioded to prevent damage to the crystal. avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. all nc (no connect) pins must be connected to ground. moisture-sensitive packages are shipped from the factory dry-packed. handling instructions listed on the package label must be followed to prevent damage during reflow. refer to the ip c/jedec j-std-020 standard for moisture-sensitive device (msd) classifications. absolute maximum ratings stresses above the ratings listed below can cause perman ent damage to the IDT1339. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended dc operating conditions note a: operating voltages without a back up supply connected. note b: when a back up supply voltage is connected choose proper part number 1339-2 or 1339-31 depending upon the back up supply voltage. item symbol rating all inputs and outputs -0.3 v to +6.0 v storage temperature -55 to +125 ? c soldering temperature 260 ? c parameter symbol min. typ. max. units ambient operating temperature t a -40 +85 ? c backup supply voltage v backup 1.3 3.0 3.7 v pull-up resistor voltage (sqw/int , sda, scl), v cc = 0v v pu 5.5 v logic 1 v ih 0.8 v cc v cc + 0.3 v logic 0 v il -0.3 0.2 v cc v supply voltage IDT1339-2, note a v cc v pf 2.0 5.5 v IDT1339-31, note a v pf 3.3 5.5 power fail voltage IDT1339-2, note b v pf 1.40 1.70 1.80 v IDT1339-31, note b 2.45 2.70 2.97
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 15 IDT1339 rev s 031014 dc electrical characteristics unless stated otherwise, v cc = min to max , ambient temperature -40 to +85 ? c, note 1 dc electrical characteristics unless stated otherwise, v cc = 0v , ambient temperature -40 to +85 ? c, note 1 parameter symbol conditions min. typ. max. units input leakage i li note 2 1 a i/o leakage i lo note 3 1 a logic 0 out v cc > 2.0 v i ol IDT1339-2, note 3 3 ma logic 0 out vol = 0.4; vcc > vcc min. v cc > 2.0 v i ol IDT1339-31, note 3 3ma logic 0 out vol = 0.2 v ( v cc ); 1.8 v < v cc < 2.0 v i ol note 3 3 ma logic 0 out vol = 0.2 v ( v cc ); 1.3 v < v cc < 1.8 v i ol note 3 250 a v cc active current i cca note 4 450 a v cc standby current, note 5 i ccs v cc < 3.63 v 80 150 a 3.63 v < v cc < 5.5 v 200 trickle-charger resistor register 10h = a5h, v cc = typ, v backup = 0v r1 note 6 250 ? trickle-charger resistor register 10h = a6h, v cc = typ, v backup = 0v r2 2000 ? trickle-charger resistor register 10h = a7h, v cc = typ, v backup = 0v r3 4000 ? v backup leakage current i bklkg 25 100 na parameter symbol conditions min. typ. max. units v backup current eosc = 0, sqw off i bkosc note 7 800 1200 na v backup current eosc = 0, sqw on i bksqw note 7 1025 1400 na v backup current eosc = 1 i bkdr note 7 120 300 na
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 16 IDT1339 rev s 031014 ac electrical characteristics unless stated otherwise, v cc = min to max , ambient temperature -40 to +85 ? c, note 13 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. note 1 : limits at -40c are guaranteed by design and are not production tested. note 2 : scl only. note 3 : sda and sqw/int . note 4 : i cca ?scl at f sc max, vil = 0.0v, vih = v cc , trickle charger disabled. note 5 : specified with the i 2 c bus inactive, vil = 0.0v, vih = v cc , trickle charger disabled. note 6 : v cc must be less than 3.63 v if the 250 ? resistor is selected. parameter symbol conditions min. typ. max. units scl clock frequency f scl fast mode 100 400 khz standard mode 100 bus free time between a stop and start condition t buf fast mode 1.3 s standard mode 4.7 hold time (repeated) start condition, note 8 t hd:sta fast mode 0.6 s standard mode 4.0 low period of scl clock t low fast mode 1.3 s standard mode 4.7 high period of scl clock t high fast mode 0.6 s standard mode 4.0 setup time for a repeated start condition t su:sta fast mode 0.6 s standard mode 4.7 data hold time, notes 9, 10 t hd:dat fast mode 0 0.9 s standard mode 0 data setup time, note 11 t su:dat fast mode 100 ns standard mode 250 rise time of both sda and scl signals, note 12 t r fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 1000 fall time of both sd a and scl signals, note 12 t f fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 300 setup time for stop condition t su:sto fast mode 0.6 s standard mode 4.0 capacitive load for each bus line, note 12 c b 400 pf i/o capacitance (sda, scl) c i/o note 13 10 pf oscillator stop flag (osf) delay t osf note 14 100 ms
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 17 IDT1339 rev s 031014 note 7 : using recommended crystal on x1 and x2. note 8 : after this period, the first clock pulse is generated. note 9 : a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 10 : the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 11 : a fast-mode device can be used in a standard-mode system, but the requirement t su:dat > to 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su:dat = 1000 + 250 = 1250 ns before the scl line is released. note 12 : c b ?total capacitance of one bus line in pf. note 13 : guaranteed by design. not production tested. note 14 : the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set over the voltage range of 0.0v < v cc < v cc max and 1.3 v < v backup < 3.7 v. timing diagram
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 18 IDT1339 rev s 031014 typical operating characteristics (v cc =3.3v, t a =25 ? c) icc vs vcc (IDT1339-31) sda=gnd 0 4 8 12 16 20 2.7 3.2 3.7 4.2 4.7 5.2 supply current (ua) vcc (v) scl=400khz scl=0hz ibackup vs temperature (IDT1339-31) rs1=rs0=00 300 340 380 420 460 500 -40-200 20406080 temperature (c) supply current (na) intc=1 intc=0 oscillator frequency vs supply voltage (IDT1339-31) 32768 32768.05 32768.1 2.8 3.3 3.8 4.3 4.8 5.3 frequency (hz) oscillator supply voltage (v) freq ibackup vs vbackup (IDT1339-31) rs1=rs0=00 380 385 390 395 400 405 410 415 420 425 1.3 1.8 2.3 2.8 3.3 vbackup (v) supply current (na) intc=1 intc=0
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 19 IDT1339 rev s 031014 thermal characteristics for 8msop thermal characteristics for 8soic thermal characteristics for 16soic parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 95 ? c/w thermal resistance junction to case ? jc 48 ? c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 150 ? c/w ? ja 1 m/s air flow 140 ? c/w ? ja 3 m/s air flow 120 ? c/w thermal resistance junction to case ? jc 40 ? c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 120 ? c/w ? ja 1 m/s air flow 115 ? c/w ? ja 3 m/s air flow 105 ? c/w thermal resistance junction to case ? jc 58 ? c/w
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 20 IDT1339 rev s 031014 marking diagram (8 msop) marking diagram (8 soic) notes: 1. ?#? is the lot number. 2. ?$? is the assembly mark code. 3. ?**? is the lot sequence. 4. yyww is the last two digits of the year and week that the part was assembled. 5. ?g? denotes rohs compliant package. 6. ?i? denotes industrial grade. 7. bottom marking: country of origin if not usa. marking diagram (16 soic) 31gi yyww$ IDT1339-31dvgi 92gi yyww$ IDT1339-2dvgi IDT1339 -31dcgi #yyww$ 14 5 8 IDT1339-31dcgi IDT1339 -2dcgi #yyww$ 14 5 8 IDT1339-2dcgi 1 8 9 16 idt 1339ac-2 sri yyww**$ IDT1339ac-2sri 1 8 9 16 idt 1339ac-31 sri yyww**$ IDT1339ac-31sri
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 21 IDT1339 rev s 031014 package outline and package dimensions (8-pin soic, 150 mil. body) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c ? c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 ? 0 ? 8 ? 0 ? 8 ?
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 22 IDT1339 rev s 031014 package outline and package dimensions (8-pin msop, 3.00 mm body) package dimensions are kept current with jedec publication no. 95 *for reference only. controlling dimensions in mm. ?e? dimension is 4.9mm basic per jedec standard; tolerance is 0.25mm or 0.0098 inches millimeters inches* symbol minmaxminmax a -- 1.10 -- 0.043 a1 0.05 0.15 0.002 0.006 a2 0.81 0.91 0.032 0.036 b 0.22 0.38 0.008 0.015 b1 0.22 0.33 0.008 0.013 c 0.13 0.18 0.005 0.009 c1 0.13 0.18 0.005 0.007 d 2.90 3.10 0.114 0.122 e 4.90 basic 0.193 basic e1 2.90 3.10 0.114 0.122 e 0.65 basic 0.0256 basic l 0.445 0.648 0.0175 0.0255 1 0 ? 6 ? 0 ? 6 ?
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 23 IDT1339 rev s 031014 package outline and package dimensions (16-pin soic, 300 mil body) package dimensions are kept current with jedec publication no. 95 index area 1 2 16 d e1 e seating plane a 1 a a 2 e - c - b aaa c ? c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a -- 2.65 -- 0.104 a1 0.10 -- 0.0040 -- a2 2.05 2.55 0.081 0.100 b 0.33 0.51 0.013 0.020 c 0.18 0.32 0.007 0.013 d 10.10 10.50 0.397 0.413 e 10.00 10.65 0.394 0.419 e1 7.40 7.60 0.291 0.299 e 1.27 basic 0.050 basic l 0.40 1.27 0.016 0.050 ? 0 ? 8 ? 0 ? 8 ? aaa - 0.10 - 0.004
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 24 IDT1339 rev s 031014 ordering information the IDT1339 packages are rohs compliant. packages wi thout the integrated cr ystal are pb-free; pack ages that include the integrated crystal (as designated with a ?c? before the dash number) may incl ude lead that is exempt under rohs requirements. the lead fini sh is jesd91 category e3. ?a? is the device revision designator and wi ll not correlate to th e datasheet revision. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 1339-2dvgi see page 20 tubes 8-pin msop -40 to +85 ? c 1339-2dvgi8 tape and reel 8-pin msop -40 to +85 ? c 1339-2dcgi tubes 8-pin soic -40 to +85 ? c 1339-2dcgi8 tape and reel 8-pin soic -40 to +85 ? c 1339ac-2srgi tubes 16-pin soic -40 to +85 ? c 1339ac-2srgi8 tape and reel 16-pin soic -40 to +85 ? c 1339-31dvgi tubes 8-pin msop -40 to +85 ? c 1339-31dvgi8 tape and reel 8-pin msop -40 to +85 ? c 1339-31dcgi tubes 8-pin soic -40 to +85 ? c 1339-31dcgi8 tape and reel 8-pin soic -40 to +85 ? c 1339ac-31srgi tubes 16-pin soic -40 to +85 ? c 1339ac-31srgi8 tape and reel 16-pin soic -40 to +85 ? c
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 25 IDT1339 rev s 031014 revision history rev. date originator description of change a 06/26/07 s. sharma new device. preliminary release. b 11/01/07 j. sarma updated ordering info for 16-pin soic package. c 01/17/08 j. sarma added 8-pin soic package; updated ?power- up/down characteristics? table; updates to ?absolute maximum ratings? table. d 02/11/08 j. sarma combined part numbers for 1339-3 and 1339-33 into one part number: 1339-31. e 03/28/08 j.sarma added new note to part ordering information pertaining to rohs compliance and pb-free devices. f 05/18/08 j.sarma changed the part number for the 16pin soic package from IDT1339c-31sogi to IDT1339c-31sri and the IDT1339c-2sogi changed to IDT1339c-2sri g 08/04/08 j.sarma removed ?preliminary?; removed ul statement from pin 3 description. h 11/20/08 j.sarma updated block diagram, detailed description section(s), operating circuit diagram, and typical operating characteristics diagrams. i 12/03/08 j.sarma updated block diagram, features bullets, pin descriptions, typical operating characteristics diagrams; added marking diagrams. j 11/10/09 added ?handling, pcb layout, and assembly? section. k 03/29/10 s.s. added ?timeout? paragraph on page 11. l 7/30/10 l.p. added underwriters laboratory recognition. m 04/13/11 l. p. updated supply current specifications. n 06/03/11 d.c. updated package drawing and dimensions for 8msop. p 06/05/12 d.c. 1. updated top-side marking for dvg package from 'yww$' to 'yyww$' q 09/20/12 j. chao 1. moved all from fab4 to tsmc. qa requested change in the marking of only the 16-pin soic device with internal crystal to add "a" due to the fact that tsmc uses a different crystal than fab4. notification of a change in orderables was initiated with pcn a1208-06. 2. updated 16-pin soic marking diagram and ordering information to include "a". r 12/10/12 j. chao updated orderable parts - added ?g? to 16-pin soic parts with sri/sri8. new part numbers for 16-pin soic will read as srgi and srgi8. s 07/01/13 j. chao updated typ. and max. values for vbackup parameters in dc char table per latest tsmc data. s 03/10/14 j. chao updated tvccf from 300 s to 3 ms. added associated note.
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